ASCENDSemiconductor4Mx4 EDOData sheet
Rev.1Page 1
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AD 40 4M 4 2 V S A – 5AscendSemiconductorEDO/FPMD-RAMBUSDDRSDRAMDDRSGRAMSGRAM SDRAM : 40: 41: 42: 43: 46: 48Density16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega BitOrganization 4: x4 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32Refresh 1 : 1K 8 : 8K 2 : 2K 6 :16K 4 : 4K Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 6ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz )EDO : -5 (50 ns) -6 (60 ns)Revision A : 1st B : 2nd C : 3rd D :4thInterface V: 3.3V R: 2.5V PackageC: CSP B: uBGAT: TSOP Q: TQFPP: PQFP ( QFP )L: LQFP S: SOJRev.1Page 2
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Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).Features
• Single 3.3V(±10%) only power supply• High speed tRAC acess time: 50/60ns• Low power dissipation
- Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access• I/O level: CMOS level (Vcc = 3.3V)
• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)• 4 refresh modesh: - RAS only refresh
- CAS - before - RAS refresh- Hidden refresh- Self-refresh(S-version)
Rev.1Page 3
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Pin Configuration
26/24-PIN 300mil Plastic SOJ
26/24-PIN 300mil Plastic TSOP (ll)
VCCDQ1DQ2 WERAS NC A10 A0 A1 A2 A3VCC
1234568910111213
26 25
24232221191817161514
VSSDQ4DQ3CASOEA9A8A7A6A5A4VSS
VCCDQ1DQ2 WERAS NC A10 A0 A1 A2 A3VCC
1234568910111213
262524232221191817161514
VSSDQ4DQ3CASOEA9A8A7 A6A5 A4VSS
AD404M42VTAD404M42VSPin Description Pin NameA0-A10
Function
Address inputs
- Row address A0-A10- Column address A0-A10- Refresh address A0-A10Data-in / data-outRow address strobeColumn address strobeWrite enableOutput enablePower (+ 3.3V)Ground
DQ1~DQ4RASCASWEOEVccVss
Rev.1Page 4
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Block Diagram
WE
CAS
CONTROL
LOGIC
DATA-IN BUFFER
DQ1..DQ4
NO. 2 CLOCKGENERATOR
DATA-OUTBUFFER
OE
COLUMNADDRESSBUFFERS (11)
A0A1A2A3A4A5A6A7A8A9
ROWDECODERCOLUMNDECODER
REFRESHCONTROLLER
2048
SENSE AMPLIFIERS
I/O GATING
REFRESHCOUNTER
2048x42048A10
ROWADDRESSBUFFERS (11)
2048x2048x4MEMORYARRAY
RAS
NO. 1 CLOCKGENERATOR
VccVss
Rev.1Page 5
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TRUTH TABLE
ADDRESSES
FUNCTION
RAS
STANDBYREAD
WRITE: (EARLY WRITE )READ WRITEEDO-PAGE-MODE READ
1st Cycle2nd Cycle
EDO-PAGE1st Cycle
MODE WRITE
2nd Cycle1st CycleEDO-
PAGE-MODE
READ-WRITE2nd CycleHIDDENREFRESH
READWRITE
RAS-ONLY REFRESHCBR REFRESH
HLLLLLLLLLL→H→LL→H→L
LH→L
CASH→XLLLH→LH→LH→LH→LH→LH→LLLHL
WEXHLH→LHHLLH→LH→LHLXH
OEXLXL→HLLXX
ROWXROWROWROWROWn/aROWn/aROWn/aROWROWROWX
COLXCOLCOLCOLCOLCOLCOLCOLCOLCOLCOLCOLn/aX
High-ZData-OutData-ln
Data-Out,Data-lnData-OutData-OutData-InData-In
Data-Out, Data-InData-Out, Data-InData-OutData-InHigh-ZHigh-Z
1
DQS
Notes
L→HL→H
LXXX
Notes: 1. EARLY WRITE only.
Rev.1Page 6
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Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss Supply voltage relative to Vss Short circuit output currentPower dissipationOperating temperatureStorage temperature
SymbolVTVCCIOUTPDTOPTTSTG
Value-0.5 to + 4.6-0.5 to + 4.6
501.00 to + 70-55 to + 125
UnitVVmAW
°C°C
Recommended DC Operating Conditions
Parameter/ConditionSymbol
Min
3.3 Volt Version
Typ3.3
Max
3.6
Unit
Supply Voltage
Input High Voltage, all inputsInput Low Voltage, all inputs
VCCVIHVIL
3.02.0-0.3
VVV
-VCC + 0.3-0.8
Capacitance
±10%, f = 1MHzTa = 25°C, VCC = 3.3V
Parameter
Input capacitance (Address)
Input capacitance (RAS, CAS, OE, WE)Output capacitance
(Data-in, Data-out)
SymbolCI1CI2CI/O
Typ ---
Max577
UnitpFpFpF
Note111, 2
Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = VIH to disable Dout.
Rev.1Page 7
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DC Characteristics :
(Ta = 0 to 70°C, VCC = + 3.3V ±10%, VSS = 0V)
ParameterSymbolTest Conditions
Min
AD404M42V-5Max120
Min--6Max110
UnitNotes
Operating current
ICC1
RAS cyclingCAS, cycling tRC = minLVTTL interfaceRAS, CAS = VIH Dout = High-ZCMOS interfaceRAS, -0.2VCAS≥VCCDout = High-Z
-mA1, 2
Low
powerS-version
ICC2
-0.5-0.5mA
-0.15-0.15mA
Standby Current
Standardpowerversion
LVTTL interfaceRAS, CAS = VIH Dout = High-ZCMOS interfaceRAS,CAS≥VCC-0.2VDout = High-Z
-2-2mA
-0.5-0.5mA
RAS- only refresh currentEDO page mode currentCAS- before- RAS refresh current
Self- refresh current(S-Version)
ICC3ICC4ICC5
RAS cycling, CAS = VIH tRC = mintPC = mintRC = min
RAS, CAS cycling
---
12090120
---
11080110
mAmAmAµA
1, 21, 31, 2
- 550 - 550ICC8 tRASS≥100µs
Rev.1Page 8
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DC Characteristics :
(Ta = 0 to 70°C, VCC= +3.3V ±10%, VSS= 0V)
AD404M42V
-5
ParameterInput leakage currentOutput leakage currentOutput high VoltageOutput low voltageNotes:
1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition.2. Address can be changed once or less while RAS = VIL.
3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
SymbolILIILOVOHVOL
Test Conditions0V≤Vin≤VCC + 0.3V0V≤Vout≤VCC + 0.3VDout = DisableIOH = -2mAIOL = +2mA
2.4--0.4
2.4--0.4
VV
Min-5-5
Max
55
Min-5-5-6Max
55
µAµAUnit
Notes
Rev.1Page 9
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AC Characteristics
(Ta = 0 to + 70°C, Vcc = 3.3V %, V±10ss = 0V) *1, *2, *3, *4
Test conditions
• Output load: one TTL Load and 100pF (VCC = 3.3V ±10%)• Input timing reference levels:
VIH = 2.0V, VIL = 0.8V (VCC = 3.3V ±10%)• Output timing reference levels:VOH = 2.0V, VOL = 0.8V
Read, Write, Read- Modify- Write and Refresh Cycles(Common Parameters)
AD404M42V -5
Parameter
Random read or write cycle timeRAS precharge time
CAS precharge time in normal modeRAS pulse widthCAS pulse widthRow address setup timeRow address hold timeColumn address setup timeColumn address hold timeRAS to CAS delay time
RAS to column address delay timeColumn address to RAS lead timeRAS hold timeCAS hold time
CAS to RAS precharge timeOE to Din delay timeTransition time (rise and fall)Refresh period
Refresh period (S- Version)CAS to output in Low- ZCAS delay time from DinOE delay time from Din
SymboltRCtRPtCPNtRAStCAStASRtRAHtASCtCAHtRCDtRADtRALtRSHtCSHtCRPtOEDtTtREFtREFtCLZtDZCtDZO
Min84301050808081210258385121--000
Max
---1000010000
----3725-----5032128---Min1044010601001001014123010405151--000-6Max
---1000010000
----4530-----5032128---nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsmsnsnsns
111089756
Unit
Notes
Rev.1Page 10
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Read Cycle
AD404M42V -5
Parameter
Access time from RASAccess time from CAS
Access time from column addressAccess time from OERead command setup timeRead command hold time to CASRead command hold time to RASOutput buffer turn-off time
Output buffer turn-off time from OE
SymboltRACtCACtAAtOEAtRCStRCHtRRHtOFFtOEZ
Min
----00000
Max50142512---1212
Min
----00000-6Max60153015---1515
nsnsnsnsnsnsnsnsns
710, 161617171213, 14 14, 15
Unit
Notes
Write Cycle
AD404M42V-5
Parameter
Write command setup time Write command hold timeWrite command pulse widthWrite command to RAS lead timeWrite command to CAS lead timeData-in setup timeData-in hold timeWE to Data-in delay
SymboltWCStWCHtWPtRWLtCWLtDStDHtWED
Min
0881380810
Max
--------Min
01010151001010-6Max
--------nsnsnsnsnsnsnsns
19197, 18
Unit
Notes
Rev.1Page 11
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Read- Modify- Write Cycle
AD404M42V
-5
Parameter
Read-modify- write cycle timeRAS to WE delay timeCAS to WE dealy time
Column address to WE delay timeOE hold time from WE
SymboltRWCtRWDtCWDtAWDtOEH
Min1086426398
Max
-----Min13377324710-6Max
-----nsnsnsnsns
181818
Unit
Notes
Refresh Cycle
AD404M42V -5
Parameter
CAS setup time (CBR refresh) CAS hold time (CBR refresh)RAS precharge to CAS hold timeRAS pulse width (self refresh)RAS precharge time (self refresh)CAS hold time (CBR self refresh)WE setup timeWE hold time
Symbol
tCSRtCHRtRPCtRASStRPStCHStWSRtWHR
Min
58510090-50010
Max
--------Min
5105100110-50010-6Max
--------Unitnsnsnsµsnsnsnsns
107Notes
Rev.1Page 12
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EDO Page Mode Cycle
AD404M42V
-5
Parameter
EDO page mode cycle time
EDO page mode CAS precharge timeEDO page mode RAS pulse widthAccess time from CAS prechargeRAS hold time from CAS prechargeOE high hold time from CAS highOE high pulse width
Data output hold time after CAS lowOutput disable delay from WE
WE pulse width for output disable when
CAS high
SymboltPCtCPtRASPtCPAtCPRHtOEHCtOEPtCOHtWHZtWPZ
Min201050-30510537
Max
--10530----10-Min251060-35510537-6Max
--10535----10-Unitnsnsnsnsnsnsnsnsnsns
2010, 14Notes
EDO Page Mode Read Modify Write Cycle
AD404M42V-5
Parameter
EDO page mode read- modify- write cycle CAS precharge to WE delay time
EDO page mode read- modify- write cycle time
SymboltCPWtPRWC
Min4556
Max
--Min5568-6Max
--Unitnsns
Notes10
Rev.1Page 13
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Notes :
1. AC measurements assume tT = 2ns.
µs 2. An initial pause of 100 is required after power up, and it followed by a minimum of eight
initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internalrefresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.
3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data tothe device.
4. All the VCC and VSS pins shall be supplied with the same voltages. 5. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle.6. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle.
7. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS .
8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS .
11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition
time is measured between VIH and VIL.
≤RCD(max) and tRAD t≤RAD(max). If tRCD or tRAD is greater than the maximum 12. Assumes that tRCD t
recommended value shown in this table, tRAC exceeds the value shown. 13. Assumes that (max) andtRCD≥tRCDtRAD
≤tRAD(max).
14. Access time is determined by the maximum of tAA, tCAC, tCPA. 15. Assumes that (max) and (max). tRCD≤tRCDtRAD≥tRAD 16. Either tRCH or tRRH must be satisfied for a read cycle.
17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high
impedance). tOFF is determined by the later rising edge of RAS or CAS.
18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If (min), the cycle is an early write cycle and thetWCS≥tWCSdata out will remain open circuit (high impedance) throughout the entire cycle. If (min),tRWD≥tRWDtCWD
≥tCWD(min), (min) and (min), the cycle is a read-modify-write andtAWD≥tAWDtCPW≥tCPW
the data output will contain data read from the selected cell. If neither of the above sets of conditionsis satisfied, the condition of the data output (at access time) is indeterminate.
19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a
delayed write or a read-modify-write cycle.
20. tRASP defines RAS pulse width in EDO page mode cycles.
Rev.1Page 14
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Timing Waveforms
• Read Cycle
tRCtRAS
tRP
RAS
t
CRP
t
CSH
t
RCD
tT
t
RSHt
CAS
t
CPN
CASt
RADtRAL
tASRt
RAHRow
t
ASCt
CAHColumn
t
RRH
ADDRESS
t
RCSt
RCH
WEOE
tOEAt
CAC
tAA
t
RAC
tOEZtOFFtOFF
DQ1~DQ4
tCLZ
Note : = don’t care = Invalid DoutDOUT
Rev.1Page 15
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•Early Write Cycle
t
RCtRAS
tRP
RAS
t
CSH
t
RCD
tTt
RSHt
CAS
t
CRP
t
CPN
CAS
t
RAD
t
ASR
t
RAHRow
t
ASCt
CAHColumn
tRAL
ADDRESS
tRALtWCStWCH
WEtDS
tDH
DQ1~DQ4
DIN
Rev.1Page 16
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• Delayed Write Cycle
t
RCtRAS
tRP
RAS
t
CSH
t
RCD
tT
t
RSHtCAS
t
CRPt
CPN
CAS
t
ASRt
RAHt
ASCt
CAH
ADDRESS
RowColumn
tCWL
tRCS
tRWLtWP
WEtOED
tOEH
OEtDS
tDS
tDH
DQ1~DQ4
OPEN
DIN
Rev.1Page 17
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• Read - Modify - Write Cycle
t
RWCtRAS
tRPRAStTt
RCD
t
CAS
t
CRPt
CPN
CAS
t
RAD
tASR
Row
t
RAH
t
ASC
t
CAH
ADDRESSColumntRCSt
CWDt
AWDtRWDt
CWLt
RWLtWP
WEt
DZC
tDS
tDH
DQ1~DQ4
OPEN
DIN
t
DZO
tOED
tOEH
OEtOEAtCACtAA
tOEZ
tRAC
DQ1~DQ4
DOUT
Rev.1Page 18
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• EDO Page Mode Read Cycle
t
RASPt
CPRHtRP
RASt
CRP
t
CSH
t
CRP
t
RCD
t
CAS
tCP
tPC
t
CAS
tCP
t
RSHt
CAS
t
CPN
CAS
t
RAD
t
ASR
t
RAHt
ASCt
CAH
tASC
t
CAH
tASCtRALt
CAH
ADDRESS
RowColumn 1Column 2Column NRow
tRCS
t
RRHtRCHWEWE
tOEHC
tOEA
t
OEP
tOEA
OEOE
tRAC
tAA
tCPAtAA
tCPAtAAtOEZ
tCAC
tCACtCOH
tCAC
tOFF
tOEZ
tOFF
DQ1~DQ4
DOUT 1
DOUT 2
DOUT N
OPEN
Rev.1Page 19
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• EDO Page Mode Early Write Cycle
t
RASP
t
RP
RAS
tT
t
CSHt
RCD
tCAS
tCP
tPC
t
CAS
tCP
t
RSHtCAS
t
CRPt
CPN
CAS
t
ASR
t
RAH
t
ASC
t
CAHt
ASCt
CAHt
ASCt
CAH
ADDRESS
RowColumn 1Column 2Column N
tWCS
tWCHtWCStWCHtWCStWCH
WEWE
tDStDHtDStDHtDStDH
DQ1~DQ4
DIN 1DIN 2DIN N
Rev.1Page 20
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• EDO Page Mode Read-Early-Write Cycle
tRASP
t
CPRHtRP
RASt
CRP
t
CSH
t
CRP
t
RCD
t
CAS
tCP
tPC
t
CAS
tCP
t
RSHt
CAS
t
CPN
CAS
t
CSHt
RAD
t
ASR
t
RAHt
ASCt
RAH
tASC
t
CAH
tASCtCALtRALt
CAH
ADDRESS
RowColumn 1Column 2Column NRow
tRCS
t
RCH
t
WCSt
WCH
WEWE
tOEA
t
WED
OEOE
tRAC
tAA
tCPAtAA
tWHZ
tCAC
tCOH
tCACtDS
Data
Doutput 2
DataInput N
tDH
DQ1~DQ4
OPEN
Data
Doutput 1
Rev.1Page 21
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• EDO Page Mode Read-Modify-Write Cycle
tRASP
tCPRH
tRP
RASt
T
t
RCD
t
CAS
tCPtPRWC
tCAS
tCPt
CAS
t
CRP
CASt
RAD
tASR
t
RAH
t
ASC
t
CAH
tASC
t
CAHColumn 2
t
CWL
t
CPWtAWDt
CWD
t
CWLt
RCS
tRALtASCt
CAH
ADDRESS
RowColumn 1Column 1t
RWDt
AWDt
CWD
Column N
t
CWLt
CPWtAWDt
CWD
t
RWL
t
RCS
WEWE
tRCS
tWPtDS
tDZC
tDH
OPEN
tDZCtWPtDS
tDH
OPEN
OPENtDZC
tWPtDS
tDH
DQ1~DQ4
DIN 1DIN 2DIN N
tDZO
tDZO
tOED
tOEH
tOED
tOEH
tDZOtOED
tOEH
OE
tOEAtCACtRAC
tAA
tOEZ
tOEA
tCACtAAtCPA
tOEZ
tCACtAAtCPA
tOEZtOEA
DQ1~DQ4
DOUT 1
DOUT 2
DOUT N
Rev.1Page 22
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• Read Cycle with WE Controlled Disable
RAS
t
CSH
t
RCD
tT
t
CAS
CASt
RAD
tASR
t
RAHt
ASC
t
CAH
ADDRESS
RowColumn
tRCS
tRCHtWPZ
WEtWHZ
OEtDS
tOEAtCAC
tAA
tRAC
tOEZDQ1~DQ4
tCLZ
DOUT
Rev.1Page 23
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RAS-Only Refresh Cycle
tRCtRAS
tRP
RAS
tT
tCRP
tRPC
tCRP
CAS
tASR
tRAH
ADDRESS
ROW
tOFF
OPEN
DQ1~DQ4
CAS-Before-RAS Refresh Cycle
tRC
tRP
tRAStRPtRAS
tRC
tRP
RAStRPC
tTtCSR
tCHR
tRPC
tCSR
tCHR
tCRP
CAS
tWSR
tWHR
tWSR
tWHR
WEtOFF
OPEN
DQ1~DQ4
Rev.1Page 24
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CBR Self-Refesh Cycle
tRASStRPS
RAStRPCtCSR
tCHS
CAStOFF
DQ1~DQ4
tWSR
tWHR
High lmpedance
WE
OPENRev.1Page 25
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• Hidden Refresh Cycle
tRCtRAS
(READ)
tRC
tRP
tRAS
(REFRESH)
tRC
tRPtRAS
(REFRESH)
tRP
RAS
tT
tCHR
tRSH
tRCD
tCAS
tCRP
CAS
tRADtASR
tRAHtASC
tRALtCAH
ADDRESS
ROWCOlumn
tRRH
t RCS
tRCH
WEOEtOEAtCAC
tAA
tRAC
tOEZtOFFtOFF
DQ1~DQ4
D OUT
Rev.1Page 26
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Ordering information
Part NumberAD404M42VSA-5AD404M42VSA-6AD404M42VTA-5AD404M42VTA-6
AD404M42VSA-5• AD • 40 • 4M4 • 2
• V Access time50 ns60 ns50 ns60 ns
Package
300mil 26/24-PinPlastic SOJ
TSOP II
• Ascend Memory Product• Device Type
• Density and Organization• Refresh Rate, 2: 2K Refresh• T: 5V, V: 3.3V
• Package Type (S : SOJ, T : TSOP II)• Version
• Speed (5: 50 ns, 6: 60 ns)
• S• A
• 5
Packaging information• 300 mil, 26/24-Pin Plastic SOJ
DDIMAA1A2bb1b2cc1DEE1E2eR1MILLIMETERSINCHESMIN.NOM.MAX.MIN.NOM.MAX.3.253.513.760.1280.1380.1482.08------0.082------2.54 REF.0.100 REF.0.410.410.660.180.1817.02---0.46---0.510.480.810.0160.0160.0260.0070.0070.670---0.018---0.0200.0190.03216813b26211914b1c1cE1EBASE METALWITH PLATING---0.30---0.2817.1517.278.51 BASIC7.497.627.756.78 BASIC1.27 BASIC0.76---1.02---0.0120.011---0.6750.6800.335 BASIC0.2950.3000.3050.267 BASIC0.050 BASIC0.030---0.040SECTION B-BCL0.025\" MIN.A2AA1E2BBNOTE:1. CONTROLLING DIMENSION : INCHES2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.MOLD PROTRUSION SHALL NOT EXCEED 0.006\"(0.15mm) PER SIDE.DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01\"(0.25mm) PER SIDE.3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION ORINTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005\"(0.127mm)DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTHTO LESS THAN 0.001\"(0.025mm) BELOW b2 MIN.eb2b0.007\"M4-e0.004\"RAD R1SEATING PLANERev.1Page 27
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• 300 mil, 26/24-Pin TSOP II
DIMAA1A2bb1cc1DZDeEE1LRR1MILLIMETERSMIN.---0.050.950.300.300.120.1217.01NOM.------1.00---0.40---0.1517.140.95 REF.1.27 BASIC9.027.490.400.120.129.227.620.50------9.427.750.600.25---0.3550.2950.0160.0050.005MAX.1.200.151.050.520.450.210.1617.27MIN.---0.0020.0370.0120.0120.0050.0050.670INCHESNOM.------0.039---0.016---0.0060.6750.050 BASIC0.3630.3000.020------0.3710.3050.0240.010---(ZD)AMAX.0.0470.0060.0410.0200.0180.008(0.006)0.68016D813E1EA126211914A2RAD R1RAD RBBcDETAIL Abb1L0 ~50.0374 BASICSECTION B-Bc1cBASE METALWITH PLATINGDETAIL ANOTE:1. CONTROLLING DIMENSION : MILLIMETERS2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006\") PER SIDE.DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01\") PER SIDE.3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TOBE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWERTHAN THE MIN b DIMENSION BY MORE THAN 0.07mm.4-1.27REF.b0.200(0.008\")MeSEATING PLANE0.100(0.004\")Rev.1Page 28
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