Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications do not apply to ADuM1400W, ADuM1401W, and ADuM1402W automotive grade versions. Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent Output Supply Current per Channel, Quiescent ADuM1400 Total Supply Current, Four Channels2 DC to 2 Mbps
VDD1 Supply Current VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current VDD2 Supply Current
90 Mbps (CRW Grade Only) VDD1 Supply Current VDD2 Supply Current
ADuM1401 Total Supply Current, Four Channels2 DC to 2 Mbps
VDD1 Supply Current VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current VDD2 Supply Current
90 Mbps (CRW Grade Only) VDD1 Supply Current VDD2 Supply Current
ADuM1402 Total Supply Current, Four Channels2 DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only) VDD1 or VDD2 Supply Current 90 Mbps (CRW Grade Only) VDD1 or VDD2 Supply Current For All Models Input Currents
Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages
Symbol
IDDI (Q) IDDO (Q)
IDD1 (Q) IDD2 (Q)
IDD1 (10) IDD2 (10)
IDD1 (90) IDD2 (90)
IDD1 (Q) IDD2 (Q)
IDD1 (10) IDD2 (10)
IDD1 (90) IDD2 (90)
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IDD1 (90), IDD2 (90)
IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH VIL, VEL
VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL PW
tPHL, tPLH PWD tPSK
tPSKCD/tPSKOD
Min −10
1.6
(VDD1 or VDD2) − 0.1 (VDD1 or VDD2) − 0.4 1 50
Typ 0.26 0.11 1.2 0.5 4.5 1.4 37 11 1.0 0.7 3.7 2.2 30 18 0.9 3.0 24
+0.01 3.0 2.8 0.0 0.04 0.2 75 11
Test Conditions
DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq.
5 MHz logic signal freq. 5 MHz logic signal freq.
45 MHz logic signal freq. 45 MHz logic signal freq.
DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq.
5 MHz logic signal freq. 5 MHz logic signal freq.
45 MHz logic signal freq. 45 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
45 MHz logic signal freq.
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
V 0.4 V V IOx = −20 µA, VIx = VIxH V IOx = −3.2 mA, VIx = VIxH 0.1 V IOx = 20 µA, VIx = VIxL 0.1 V IOx = 400 µA, VIx = VIxL 0.4 V IOx = 3.2 mA, VIx = VIxL 1000 ns CL = 15 pF, CMOS signal levels Mbps CL = 15 pF, CMOS signal levels 100 ns CL = 15 pF, CMOS signal levels 40 ns CL = 15 pF, CMOS signal levels ps/°C CL = 15 pF, CMOS signal levels 50 ns CL = 15 pF, CMOS signal levels 50 ns CL = 15 pF, CMOS signal levels Max 0.31 0.14 1.9 0.9 6.5 2.0 65 15 1.6 1.2 5.4 3.0 52 27 1.5 4.2 39 +10
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA µA
SWITCHING SPECIFICATIONS
ADuM1400ARW/ADuM1401ARW/ADuM1402ARW Minimum Pulse Width3 Maximum Data Rate4 Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature Propagation Delay Skew6
Channel-to-Channel Matching7
Rev. L | Page 6 of 31
ADuM1400/ADuM1401/ADuM1402
Parameter
ADuM1400WTRWZ/ADuM1401WTRWZ/ ADuM1402WTRWZ Minimum Pulse Width3 Maximum Data Rate4 Propagation Delay5
Pulse Width Distortion, |tPLH − tPHL|5
Change vs. Temperature Propagation Delay Skew6
Channel-to-Channel Matching, Codirectional Channels7
Channel-to-Channel Matching, Opposing-Directional Channels7 For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
Output Enable Propagation Delay (High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic High Output8
Common-Mode Transient Immunity at Logic Low Output8 Refresh Rate
Input Dynamic Supply Current per Channel9 Output Dynamic Supply Current per Channel9
12
Data Sheet
Min
Typ
Max Unit
Test Conditions
Symbol
PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD
10 18
27 5
100 34 3 15 3 6
ns Mbps ns ns ps/°C ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
tPHZ, tPLH tPZH, tPZL tR/tF |CMH| |CML| fr IDDI (D) IDDO (D)
6 6 2.5 35 35 1.2 0.19 0.05
8 8
ns ns ns kV/µs kV/µs Mbps mA/Mbps mA/Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
25 25
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400W/ADuM1401W/ADuM1402W channel configurations. 3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. L | Page 12 of 31
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